Unexpected Latchup Risk Observed in FDSOI Technology – Analysis and Prevention Techniques

Abstract

This paper reports an un-expected latchup scenario identified when utilizing the forward body bias (FBB) technique in fully depleted silicon-on-insulator (FDSOI) technology. It was found that a parasitic silicon controlled rectifier (SCR) can be formed between p-well/deep n-well/p-sub/n-well which is different from the conventional SCR observed in bulk CMOS technology (p+/n-well/p-sub/n+). The vertical injection mechanism from p-well emitter to deep n-well base and n-well emitter to p-sub base, larger emitter injection area, and larger overdrive voltage due to latchup qualification methodology imposes significant challenges in the guard ring design. Through well calibrated technology computer aided design (TCAD) simulations, the risk is systematically studied and various prevention methods like guard ring design, deep n-well to n-well distance and series resistor are explored and design guidelines for various supply domains are proposed.