Modeling of the threshold voltage variation for a stressed submicronic MOSFET

Abstract

A threshold voltage model for stressed submicron NMOS transistors is proposed. Stress conditions are chosen in a manner such that the interface states generated by hot electron injection at the Si-SiO/sub 2/ interface are dominant. The stress-generated defects vary with time. They are simulated by a spatial and temporal Gaussian distribution centered close to the extremity of the channel near the drain. The Gaussian parameters (standard deviation and maximum) vary according to the stress. Calculating the minimum surface potential by solving the two dimensional Poisson's equation (2-D) and taking into account the defect distribution evolution during stress time, the model is derived. Simulation results of threshold voltage are compared with experimental data to verify the validity of the modeling. The fitting parameters of the experimental results by the simulation curves allow us to obtain interesting information about the amount and distribution of charge injected at the Si-SiO/sub 2/ interface.