Floorplanning Multiple Reticles for Multi-project Wafers

Abstract

Floorplanning chips in more than one reticle for multi-project wafers has not been investigated. In this paper, we propose two approaches to this problem. We first formulate this problem with preselected reticle sizes as a mixed-integer linear programming (MILP) model. We then propose a compatibility-driven B*-tree dissection search (CBTDS) heuristic for it. Experiments for floorplanning chips in two reticles show that the MILP model is too complex to render good results, while CBTDS is very effective and efficient. Compared to a naive solution, CBTDS obtains a floorplan that uses 37% fewer wafers