B. Govoreanu, P. Blomme, K. Henson, J. van Houdt, K. De Meyer
{"title":"An investigation of the electron tunneling leakage current through ultrathin oxides/high-k gate stacks at inversion conditions","authors":"B. Govoreanu, P. Blomme, K. Henson, J. van Houdt, K. De Meyer","doi":"10.1109/SISPAD.2003.1233693","DOIUrl":null,"url":null,"abstract":"An efficient yet accurate model is used for investigating tunneling of minority carriers from the inversion layer of ultrathin MOSFET structures. The model is derived from the concept of the quasibound states lifetimes, which are calculated using a transfer matrix method based on Airy functions. Comparison with experimental data is provided. Performance of high-k materials is discussed and an investigation of their scalability for future CMOS technology nodes is carried out.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.2003.1233693","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
An efficient yet accurate model is used for investigating tunneling of minority carriers from the inversion layer of ultrathin MOSFET structures. The model is derived from the concept of the quasibound states lifetimes, which are calculated using a transfer matrix method based on Airy functions. Comparison with experimental data is provided. Performance of high-k materials is discussed and an investigation of their scalability for future CMOS technology nodes is carried out.