In situ characterization of CMOS post-process micromachining

Abstract

We have developed and demonstrated a new methodology for in situ monitoring and characterization of CMOS post-process micromachining utilizing integrated circuits and micromachine test-structures. In our demonstration, the circuits provide automated readout of N-well resistors surrounding each of the 140 test pit structures at up to 14,000 samples per second per device during the post-process silicon etch, and thus also provide etch progress and end point determination without extra analytical equipment. Pit sizes, surrounding layers, and topology are examined with this technique.