A UVM Verification Platform for RISC-V SoC from Module to System Level

Abstract

The study presents a module-level and system-level hierarchical UVM (Universal Verification Methodology) verification platform for a RISC-V SoC. At the module level, the platform generates constrained random stimulants to drive testing for module functions. The degree of the verification completeness is measured through the code coverage and the functional coverage. At the system level, the platform integrates the module-level environments and analyzes the interrupt and the sleep-and-wake-up characteristics of the RISC-V core. The timing correctness of the signals is checked by assertions. Compared with FPGA verification, the UVM verification platform has the advantages of shorter cycle, higher efficiency, better reusability, and makes it easier to measure the coverage. The simulation results show that the functions of the RISC-V SoC are correct and the functional coverage meets the requirements.