Simulated annealing Vs. Genetic Simulated Annealing for automatic transistor sizing

Abstract

Transistor size optimization is an important aspect of circuit design. Small and non-complex circuits can be designed easily using manual calculations and circuit simulations. But, as the complexity of circuits increases, manual design becomes too difficult and time consuming. Therefore, tools and techniques for automatic transistor sizing are of great importance in the area of circuit design. The goal of this paper is to implement Genetic Simulated Annealing algorithm as a tool for transistor sizing, and compare its performance with Simulated Annealing, one of the most popular optimization algorithm in use today. The algorithms have been tested on four different digital circuits and the results collated and compared in this paper.