Gate-to-drain/source overlap and asymmetry effects on hot-carrier generation

Abstract

An investigation of the effects of gate-to-drain/source overlap length and overlap asymmetry on the electrical and hot-carrier generation behavior is conducted on a medium-voltage (around 3 to 5 V) transistor in a 40 nm CMOS technology, using TCAD simulations calibrated with electrical measurements. The substrate current versus gate voltage is used to monitor the hot-carrier impact ionization rate. A novel numerical approach of decomposing the substrate current into its drain-side and source-side constituents is proposed, allowing to determine the junction where most of the impact ionization occurs depending on the geometrical and electrical parameters.