Wafer-level packaging for harsh environment application

Abstract

A wafer-level chip-scale packaging scheme that can withstand temperatures of 600°C and above in long-term operation is proposed. The package comprises a SOI case and a cap wafer. In the device layer of the SOI wafer, flexible springs are formed to fix target chips inside the case, so that the influence of thermal stress can be minimized. The two components are joined together through wafer bonding process under vacuum condition. Electric connection is established through Pt metallized via in SOI. Initial test results confirm the feasibility of the method.