Scaling in the third dimension -prospects for silicon-based interposer and 3D integration

Abstract

Classical constant field scaling has reached a point of diminishing returns as a result of fundamental limitations, increased process complexity and lithographic challenges. Sibased passive interposers offer the possibility of integrating heterogeneous technologies on a silicon substrate as well as the possibility synthesizing very large chips with silicon like latencies. 3D die stacking allows for an additional integration of two or more functional die with a die to die interconnect density that allows for a variety of possibilities all the way from power and I/O integration, to block and macro level integration, and in limit circuit level integration across strata. In this talk we will share the work we have doing on both interposers integrating SiGe analog die with 45nm ASICs as well as the integration of logic and memory in some key embodiments. We will discuss the challenges we face in technology, reliability, thermo-mechanical stability, design and test. Finally, we will discuss options that allow for higher levels of integration using wafer level bonding technology.