A Novel 14-Transistors Low-Power High-Speed PPM Adder

Abstract

In this paper we mainly deal with design and simulation of different redundant-binary full adder (Plus-Plus-Minus Adder) topologies using minimum number of transistors. These PPM adder topologies are simulated to evaluate their performance in total power dissipation, speed, and PDP. Compared with other PPM adder designs, the proposed novel design full adder topology features higher computing speed and lower energy (power delay product) operation. The simulation results reveal that the overall PDP for the proposed circuits have been improved by 10 % to 15 % at the supply voltage of 1.8V when compared with the reported PPM adder topologies at 0.18µm CMOS technology.