A DFM methodology to evaluate the impact of lithography conditions on the speed of critical paths in a VLSI circuit

Abstract

This paper presents a new methodology to analyze the impact of lithography conditions on a VLSI circuit. Previous methods require a flow that is partially manual, but in this work full automation is demonstrated for the first time. OPC is run on a group of NAND gates with different dummy gates and then the gate lengths are extracted using calibrated lithography models across focus and exposure. An updated netlist is extracted, and the speed and delay are measured using SPICE. The results show over a 30% speed difference over focus for the same NAND gate. Because of the differences in the surrounding layout, the relative delay between NAND gates can differ by over 25% for the same focus and exposure conditions. Simple SPICE corner models will not capture the impact of focus and exposure for deep submicron designs and more detailed analysis is required in the future