垂直集成ZnO薄膜晶体管的原子层沉积:迈向3D高封装密度薄膜电子学

Zulkarneyn Sisman, Sami Bolat, A. Okyay
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引用次数: 6

摘要

我们报道了在刚性衬底上基于原子层沉积(ALD)的三维(3D)集成ZnO薄膜晶体管(TFTs)的首次演示。器件具有高通断比(~ 106)和高有效迁移率(~ 11.8 cm2 V−1 s−1)。它也已经证明,制造的步骤导致易于稳定的电特性在tft,消除了后期制作步骤的需要。这些结果标志着我们的半导体金属氧化物垂直集成电路制造方法的潜力,需要高封装密度和高功能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Atomic Layer Deposition for Vertically Integrated ZnO Thin Film Transistors: Toward 3D High Packing Density Thin Film Electronics
We report on the first demonstration of the atomic layer deposition (ALD) based three dimensional (3D) integrated ZnO thin film transistors (TFTs) on rigid substrates. Devices exhibit high on-off ratio (∼106) and high effective mobility (∼11.8 cm2 V−1 s−1). It has also been demonstrated that the steps of fabrication result in readily stable electrical characteristics in TFTs, eliminating the need for post-production steps. These results mark the potential of our fabrication method for the semiconducting metal oxide-based vertical-integrated circuits requiring high packing density and high functionality.
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