0.1 μ m栅极、超薄膜CMOS器件采用80纳米厚埋氧化层的SIMOX衬底

Y. Omura, S. Nakashima, K. Izumi, T. Ishii
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引用次数: 91

摘要

采用高质量的SIMOX衬底和基于简单器件模型的亚四分之一微米区域的先进设计理念,成功制备了0.1 μ m栅极CMOS/SIMOX(植入式氧分离)。此外,还实现了8nm厚硅有源层的85nm栅极n型和p型mosfet /SIMOX。0.1 μ m栅极CMOS/SIMOX源极和漏极的高寄生电阻往往会增加传输延迟时间。然而,通过降低寄生电阻,可以获得延迟时间低至10 ps的0.1 μ m栅极CMOS/SIMOX器件。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
0.1- mu m-gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer
A 0.1- mu m-gate CMOS/SIMOX (separation by implanted oxygen) has been successfully fabricated using high quality SIMOX substrates and an advanced design concept for the subquarter-micron region based on a simple device model. In addition, both 85-nm-gate n- and p-MOSFETs/SIMOX with 8-nm-thick silicon active layer have been realized. High parasitic resistance in the source and drain regions of the 0.1- mu m-gate CMOS/SIMOX tends to increase the propagation delay time. However, 0.1- mu m-gate CMOS/SIMOX devices with a delay time as low as 10 ps can be obtained by reducing the parasitic resistance.<>
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