DDR/ sdr兼容SDRAM设计，具有三尺寸灵活的列冗余

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI:10.1109/VLSIC.2000.852866

T. Sakata, S. Morita, O. Nagashima, H. Noda, T. Takahashi, T. Sonoda, H. Tadokoro, H. Ichikawa, T. Adou, S. Hanzawa, M. Ohi, S. Ookuma, Y. Suzuki, H. Tanaka, K. Ishii

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引用次数: 2

摘要

提出了两种电路技术来设计双数据速率(DDR)和单数据速率(SDR)的SDRAM。通用/分离I/O方案支持DDR下的2位预取，并在SDR下中断操作，否则需要的数据总线数只有一半。SSTL/ lvttl兼容的输入缓冲器允许较窄的设置/保持时间。此外，三尺寸柔性柱冗余提高了成品率。为了评估这些技术，我们设计了一个256 mb的SDRAM，假设0.16-/spl mu/m的技术，并在167 mhz的操作下进行了模拟。

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A DDR/SDR-compatible SDRAM design with a three-size flexible column redundancy

Two circuit techniques are proposed to design a SDRAM which operates both at a double-data-rate (DDR) and a single-data-rate (SDR). The common/separated I/O scheme enables 2-bit prefetching under a DDR and interrupt operations under an SDR with half the number of data-bus lines otherwise needed. The SSTL/LVTTL-compatible input buffer allows a narrow setup/hold time. Furthermore, the three-size flexible column redundancy enhances the yield. To evaluate these techniques, a 256-Mb SDRAM has been designed assuming 0.16-/spl mu/m technology and simulated with 167-MHz operations.

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2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

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