基于0.25/spl mu/m CMOS的70V智能电源技术，深沟槽高压隔离

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI:10.1109/IEDM.2002.1175878

V. Parthasarathy, R. Zhu, V. Khemka, T. Roggenbauer, A. Bose, P. Hui, P. Rodriquez, J. Nivison, D. Collins, Z. Wu, I. Puchades, M. Butner

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引用次数: 56

摘要

提出了一种基于0.25/spl mu/m CMOS的智能电源平台，该平台基于p++衬底，具有深沟槽高压隔离，作为SOI的低成本替代方案，在不影响模拟匹配和工艺复杂性的情况下实现了显著的模拟收缩，降低了衬底寄生和70V高侧能力。

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A 0.25/spl mu/m CMOS based 70V smart power technology with deep trench for high-voltage isolation

Presents a 0.25/spl mu/m CMOS based smart power platform on a P++ substrate with a deep trench high-voltage isolation as a low-cost alternative to SOI in realizing significant analog shrink, reduction of substrate parasitics and 70V high-side capability without affecting analog matching and process complexity.

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来源期刊

Technical digest. International Electron Devices Meeting

CiteScore

4.50

自引率

0.00%

发文量