Jorge Cogo, Javier G. García, P. A. Roncagliolo, C. Muravchik
{"title":"用于SDR应用开发的高速采集和存储平台","authors":"Jorge Cogo, Javier G. García, P. A. Roncagliolo, C. Muravchik","doi":"10.1109/SPL.2011.5782619","DOIUrl":null,"url":null,"abstract":"In this work we present the design of an FPGA based platform for acquiring and storing signals for SDR applications. The system comprises an embedded RISC processor, an A/D converter, RAM memory chips and a DMA controller core. This last component was designed from scratch to meet the high data rate and bulk requirements.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":"79 1","pages":"19-24"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"High speed acquisition and storage platform for SDR applications development\",\"authors\":\"Jorge Cogo, Javier G. García, P. A. Roncagliolo, C. Muravchik\",\"doi\":\"10.1109/SPL.2011.5782619\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work we present the design of an FPGA based platform for acquiring and storing signals for SDR applications. The system comprises an embedded RISC processor, an A/D converter, RAM memory chips and a DMA controller core. This last component was designed from scratch to meet the high data rate and bulk requirements.\",\"PeriodicalId\":6329,\"journal\":{\"name\":\"2011 VII Southern Conference on Programmable Logic (SPL)\",\"volume\":\"79 1\",\"pages\":\"19-24\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-04-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 VII Southern Conference on Programmable Logic (SPL)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPL.2011.5782619\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 VII Southern Conference on Programmable Logic (SPL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPL.2011.5782619","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High speed acquisition and storage platform for SDR applications development
In this work we present the design of an FPGA based platform for acquiring and storing signals for SDR applications. The system comprises an embedded RISC processor, an A/D converter, RAM memory chips and a DMA controller core. This last component was designed from scratch to meet the high data rate and bulk requirements.