3D集成电路多芯片堆叠TSV/RDL/IPD介面器组装工艺及可靠性评估

2012 IEEE 62nd Electronic Components and Technology Conference Pub Date : 2012-07-30 DOI:10.1109/ECTC.2012.6248883

C. Zhan, P. Tzeng, J. Lau, M. Dai, H. Chien, Ching-Kuan Lee, Shang-Tsai Wu, K. Kao, Shin-Yi Huang, Chia-Wen Fan, Su-Ching Chung, Yu-wei Huang, Yu-Min Lin, Jing-Yao Chang, Tsung-Fu Yang, Tai-Hung Chen, R. Lo, M. Kao

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引用次数: 17

摘要

本研究设计并开发了一种具有TSV/RDL/IPD介面的3D集成电路系统级封装(SiP)。重点是Cu暴露，嵌入式应力传感器，非破坏性检测，热建模和测量，以及最终组装和可靠性评估。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP

In this study, a 3D IC integration system-in-package (SiP) with TSV/RDL/IPD interposer is designed and developed. Emphasis is placed on the Cu revealing, embedded stress sensors, non-destructive inspection, thermal modeling and measurement, and final assembly and reliability assessments.

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2012 IEEE 62nd Electronic Components and Technology Conference

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