A. Pal, Sushant Mittal, E. Bazizi, A. Sachid, Mehdi Saremi, B. Colombeau, G. Thareja, Samuel Lin, B. Alexander, S. Natarajan, B. Ayyagari
{"title":"MOL/BEOL空气隔离器对3nm节点寄生电容和电路性能的影响","authors":"A. Pal, Sushant Mittal, E. Bazizi, A. Sachid, Mehdi Saremi, B. Colombeau, G. Thareja, Samuel Lin, B. Alexander, S. Natarajan, B. Ayyagari","doi":"10.1109/SISPAD.2019.8870410","DOIUrl":null,"url":null,"abstract":"Impact of air-spacer at MOL and BEOL on circuit performance at 3nm technology node is studied. Our modeling results show that by introducing air-spacer at MOL and BEOL, parasitic capacitance can be reduced by 18% and circuit performance as simulated on a 31-stage ring oscillator can be improved by 6%. Other advanced parasitic improvement technologies, such as Ruthenium, also show similar performance improvement. Finally, we show that best circuit performance is achieved when these 2 technologies are combined, yielding to a circuit performance boost of 16%.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"49 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Impact of MOL/BEOL Air-Spacer on Parasitic Capacitance and Circuit Performance at 3 nm Node\",\"authors\":\"A. Pal, Sushant Mittal, E. Bazizi, A. Sachid, Mehdi Saremi, B. Colombeau, G. Thareja, Samuel Lin, B. Alexander, S. Natarajan, B. Ayyagari\",\"doi\":\"10.1109/SISPAD.2019.8870410\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Impact of air-spacer at MOL and BEOL on circuit performance at 3nm technology node is studied. Our modeling results show that by introducing air-spacer at MOL and BEOL, parasitic capacitance can be reduced by 18% and circuit performance as simulated on a 31-stage ring oscillator can be improved by 6%. Other advanced parasitic improvement technologies, such as Ruthenium, also show similar performance improvement. Finally, we show that best circuit performance is achieved when these 2 technologies are combined, yielding to a circuit performance boost of 16%.\",\"PeriodicalId\":6755,\"journal\":{\"name\":\"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)\",\"volume\":\"49 1\",\"pages\":\"1-4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SISPAD.2019.8870410\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.2019.8870410","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Impact of MOL/BEOL Air-Spacer on Parasitic Capacitance and Circuit Performance at 3 nm Node
Impact of air-spacer at MOL and BEOL on circuit performance at 3nm technology node is studied. Our modeling results show that by introducing air-spacer at MOL and BEOL, parasitic capacitance can be reduced by 18% and circuit performance as simulated on a 31-stage ring oscillator can be improved by 6%. Other advanced parasitic improvement technologies, such as Ruthenium, also show similar performance improvement. Finally, we show that best circuit performance is achieved when these 2 technologies are combined, yielding to a circuit performance boost of 16%.