Failure analysis on the mechanical property of Through-Silicon Vias interface using a cohesive zone model

Through Silicon Via(TSVs) technology is one of the most prominent feature in future microelectronic devices packaging. Since TSVs contain the interfaces of heterogeneous materials that have high CTE mismatch, and would hence produce large thermal stresses under temperature loading, often leading to mechanical failure. A failure stress mathematical model is established and the algorithm of mathematical model is prepared by using subroutine and fracture failure modeling of Cu/SiO2 interface in TSV using finite element method (FEM) with cohesive zone model as well as stiffness degradation evaluation criterion was employed. Numerical simulation results show that large thermal stresses induced by the unique feature of TSV structure and the high mismatch of CTE between silicon substrate, dielectric layer and copper core, would lead to Cu/SiO2 interface delamination and the failure mode of the interface is shear stress predominantly. The phase angle at the tip of interfacial crack is almost 80 degrees when the interface was about to crack and then it will decrease as the crack grows gradually. However, the value of phase angle is always more than 45 degrees. Additionally, the fracture analysis to the damage process of interfacial crack under mixed-mode loading has been derived based on power law of energy criterion. It is noted that the temperature cracking of the interface is reduced and the crack propagation of Cu/SiO2 will difficult as the fracture energy of cohesive elements increases.