Shireen Warnock, Chang-Lee Chen, Jeffrey Knechtl, R. Molnar, D. Yost, M. Cook, C. Stull, Ryan Johnson, C. Galbraith, J. Daulton, Weilin Hu, G. Pinelli, J. Perozek, T. Palacios, Beijia Zhang, J. Herd, C. Keast
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InAlN/GaN-on-Si HEMT with 4.5 W/mm in a 200-mm CMOS-Compatible MMIC Process for 3D Integration
In this paper we present a fully CMOS-compatible fabrication process for GaN-on-Si monolithic microwave integrated circuits (MMICs) on 200-mm-diameter wafers. This process also enables wafer-level 3D integration of GaN MMICs with Si CMOS circuits to enhance performance and functionality while reducing the size, weight, power, as well as the cost. We demonstrate our progress towards full 3D integration, including a discussion on GaN HEMT fabrication and bonding with a Si CMOS wafer. With the use of an InA1N barrier layer we show a GaN-on-Si HEMT output power of 4.5 W/mm and PAE of 53% at 10 GHz.
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