Y. Long, Jun Z. Huang, Zhongming Wei, Jun-Wei Luo, Xiangwei Jiang
{"title":"栅极控制应变抑制n型GaAs压电finfet中的关断电流","authors":"Y. Long, Jun Z. Huang, Zhongming Wei, Jun-Wei Luo, Xiangwei Jiang","doi":"10.1109/sispad.2019.8870452","DOIUrl":null,"url":null,"abstract":"The gate-controlled compressive strain induced by piezoelectric layers (piezo-layers) is used to suppress the OFF current of n-type GaAs piezoelectric FinFETs (Piezo-FinFETs). Quantum ballistic transport of n-type GaAs Piezo-FinFETs is modeled by the self-consistent Schrödinger–Poisson system. Our results suggest that n-type GaAs Piezo-FinFETs reduce OFF current by an order of magnitude for both high performance and low power applications compared with their counterparts without piezo-layers. The influences of device orientations on device performance is also investigated. The optimal device orientation of n-type GaAs Piezo-FinFETs is on the crystal surface (111).","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"38 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"OFF Current Suppression by Gate-gontrolled Strain in The N-type GaAs Piezoelectric FinFETs\",\"authors\":\"Y. Long, Jun Z. Huang, Zhongming Wei, Jun-Wei Luo, Xiangwei Jiang\",\"doi\":\"10.1109/sispad.2019.8870452\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The gate-controlled compressive strain induced by piezoelectric layers (piezo-layers) is used to suppress the OFF current of n-type GaAs piezoelectric FinFETs (Piezo-FinFETs). Quantum ballistic transport of n-type GaAs Piezo-FinFETs is modeled by the self-consistent Schrödinger–Poisson system. Our results suggest that n-type GaAs Piezo-FinFETs reduce OFF current by an order of magnitude for both high performance and low power applications compared with their counterparts without piezo-layers. The influences of device orientations on device performance is also investigated. The optimal device orientation of n-type GaAs Piezo-FinFETs is on the crystal surface (111).\",\"PeriodicalId\":6755,\"journal\":{\"name\":\"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)\",\"volume\":\"38 1\",\"pages\":\"1-4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/sispad.2019.8870452\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/sispad.2019.8870452","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
OFF Current Suppression by Gate-gontrolled Strain in The N-type GaAs Piezoelectric FinFETs
The gate-controlled compressive strain induced by piezoelectric layers (piezo-layers) is used to suppress the OFF current of n-type GaAs piezoelectric FinFETs (Piezo-FinFETs). Quantum ballistic transport of n-type GaAs Piezo-FinFETs is modeled by the self-consistent Schrödinger–Poisson system. Our results suggest that n-type GaAs Piezo-FinFETs reduce OFF current by an order of magnitude for both high performance and low power applications compared with their counterparts without piezo-layers. The influences of device orientations on device performance is also investigated. The optimal device orientation of n-type GaAs Piezo-FinFETs is on the crystal surface (111).