G. Hellings, H. Mertens, A. Subirats, E. Simoen, T. Schram, L. Ragnarsson, Marko Simicic, S.-H. Chen, B. Parvais, D. Boudier, B. Crețu, J. Machillot, V. Peña, S. Sun, N. Yoshida, N. Kim, A. Mocuta, D. Linten, N. Horiguchi
{"title":"垂直堆叠栅极-全方位水平纳米线技术中的Si/SiGe超晶格I/O finfet","authors":"G. Hellings, H. Mertens, A. Subirats, E. Simoen, T. Schram, L. Ragnarsson, Marko Simicic, S.-H. Chen, B. Parvais, D. Boudier, B. Crețu, J. Machillot, V. Peña, S. Sun, N. Yoshida, N. Kim, A. Mocuta, D. Linten, N. Horiguchi","doi":"10.1109/VLSIT.2018.8510654","DOIUrl":null,"url":null,"abstract":"This work presents Si/SiGe superlattice finFETs (FF) for 1.8V/2.5V I/O applications in vertically-stacked Gate-All-Around horizontal nanowire technology (hNW) technology. Superlattice FF have a higher ION than I/O hNW reference devices and can be more easily integrated into a GAA hNW technology than Si I/O FF. These novel I/O FET structures exhibit competitive analog performance and are superior as ESD protection devices.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"17 1","pages":"85-86"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire Technology\",\"authors\":\"G. Hellings, H. Mertens, A. Subirats, E. Simoen, T. Schram, L. Ragnarsson, Marko Simicic, S.-H. Chen, B. Parvais, D. Boudier, B. Crețu, J. Machillot, V. Peña, S. Sun, N. Yoshida, N. Kim, A. Mocuta, D. Linten, N. Horiguchi\",\"doi\":\"10.1109/VLSIT.2018.8510654\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents Si/SiGe superlattice finFETs (FF) for 1.8V/2.5V I/O applications in vertically-stacked Gate-All-Around horizontal nanowire technology (hNW) technology. Superlattice FF have a higher ION than I/O hNW reference devices and can be more easily integrated into a GAA hNW technology than Si I/O FF. These novel I/O FET structures exhibit competitive analog performance and are superior as ESD protection devices.\",\"PeriodicalId\":6561,\"journal\":{\"name\":\"2018 IEEE Symposium on VLSI Technology\",\"volume\":\"17 1\",\"pages\":\"85-86\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2018.8510654\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2018.8510654","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire Technology
This work presents Si/SiGe superlattice finFETs (FF) for 1.8V/2.5V I/O applications in vertically-stacked Gate-All-Around horizontal nanowire technology (hNW) technology. Superlattice FF have a higher ION than I/O hNW reference devices and can be more easily integrated into a GAA hNW technology than Si I/O FF. These novel I/O FET structures exhibit competitive analog performance and are superior as ESD protection devices.