{"title":"采用等离子体激活硅对硅(SOS)键合的低温MEMS工艺","authors":"T. Galchev, W. Welch, K. Najafi","doi":"10.1109/MEMSYS.2007.4433060","DOIUrl":null,"url":null,"abstract":"This paper explores the use of dielectric barrier discharge (DBD) surface activated low-temperature wafer bonding in MEMS device fabrication. Characterization of the DBD surface treatment process is included as well as analysis of the optimal bonding conditions. A new high aspect-ratio MEMS technology based on bonding two silicon wafers with an intermediate silicon dioxide layer at 400degC is presented. This silicon-on-silicon (SOS) process requires three masks and provides several advantages compared with silicon-on-glass (SOG) and silicon-on- insulator (SOI) processes, including better dimensional and etch profile control of narrow and slender MEMS structures. This is demonstrated by fabricating a 5 mum wide 30 mm long beam. Additionally, by patterning the intermediate SiO2 insulation layer before bonding, footing is reduced without any extra processing, as compared to both SOG and SOI. All SOS process steps are CMOS compatible.","PeriodicalId":6388,"journal":{"name":"2007 IEEE 20th International Conference on Micro Electro Mechanical Systems (MEMS)","volume":"18 1","pages":"309-312"},"PeriodicalIF":0.0000,"publicationDate":"2007-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Low-temperature MEMS process using plasma activated Silicon-On-Silicon (SOS) bonding\",\"authors\":\"T. Galchev, W. Welch, K. Najafi\",\"doi\":\"10.1109/MEMSYS.2007.4433060\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper explores the use of dielectric barrier discharge (DBD) surface activated low-temperature wafer bonding in MEMS device fabrication. Characterization of the DBD surface treatment process is included as well as analysis of the optimal bonding conditions. A new high aspect-ratio MEMS technology based on bonding two silicon wafers with an intermediate silicon dioxide layer at 400degC is presented. This silicon-on-silicon (SOS) process requires three masks and provides several advantages compared with silicon-on-glass (SOG) and silicon-on- insulator (SOI) processes, including better dimensional and etch profile control of narrow and slender MEMS structures. This is demonstrated by fabricating a 5 mum wide 30 mm long beam. Additionally, by patterning the intermediate SiO2 insulation layer before bonding, footing is reduced without any extra processing, as compared to both SOG and SOI. All SOS process steps are CMOS compatible.\",\"PeriodicalId\":6388,\"journal\":{\"name\":\"2007 IEEE 20th International Conference on Micro Electro Mechanical Systems (MEMS)\",\"volume\":\"18 1\",\"pages\":\"309-312\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE 20th International Conference on Micro Electro Mechanical Systems (MEMS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MEMSYS.2007.4433060\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE 20th International Conference on Micro Electro Mechanical Systems (MEMS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MEMSYS.2007.4433060","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low-temperature MEMS process using plasma activated Silicon-On-Silicon (SOS) bonding
This paper explores the use of dielectric barrier discharge (DBD) surface activated low-temperature wafer bonding in MEMS device fabrication. Characterization of the DBD surface treatment process is included as well as analysis of the optimal bonding conditions. A new high aspect-ratio MEMS technology based on bonding two silicon wafers with an intermediate silicon dioxide layer at 400degC is presented. This silicon-on-silicon (SOS) process requires three masks and provides several advantages compared with silicon-on-glass (SOG) and silicon-on- insulator (SOI) processes, including better dimensional and etch profile control of narrow and slender MEMS structures. This is demonstrated by fabricating a 5 mum wide 30 mm long beam. Additionally, by patterning the intermediate SiO2 insulation layer before bonding, footing is reduced without any extra processing, as compared to both SOG and SOI. All SOS process steps are CMOS compatible.