线性电路系统级和spice级模型的等价性检验

Kemal Çağlar Coşkun, Muhammad Hassan, R. Drechsler
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引用次数: 2

摘要

由于模拟电路及其集成到系统级芯片(SoC)中的复杂性日益增加,模拟设计和验证行业将极大地受益于使用SystemC AMS的系统级方法的扩展。与spice级模拟相比,这些可以提供超过100,000倍的速度提高,并允许在系统级与数字工具进行互操作性。然而,扩展模拟电路系统级工具的一个关键障碍是对在SystemC AMS中实现的系统级模型缺乏信心。最近成功地证明了单个拉普拉斯传递函数(LTF)系统级模型与相应的spice级模型的功能等价性。然而,这显然是不够的,因为复杂的系统包含多个LTF模块。在本文中,我们超越了单个LTF模型,即,我们开发了一种新的基于图的方法来正式检查单输入单输出(SISO)线性模拟电路(如高通滤波器(HPF))的复杂系统级和spice级表示之间的等效性。为了实现这一点,首先,我们引入了信号流图(SFG)形式的规范表示,用于从不同的建模级别对两种表示进行功能映射。这种规范化表示由输入和输出节点以及它们之间的一条边组成,其权重为LTF。其次,我们使用spice级模型的线性图建模创建SFG表示,而对于系统级模型,我们从行为描述中提取SFG。然后,我们利用三种图处理技术,即节点移除、平行边统一和自反边消除,将SFG表示转换为规范表示。这允许我们在复杂的系统级模型和spice级模型之间建立功能等价。我们通过成功地将其应用于复杂电路来证明所提出方法的适用性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits
Due to the increasing complexity of analog circuits and their integration into System-on-Chips (SoC), the analog design and verification industry would greatly benefit from an expansion of system-level methodologies using SystemC AMS. These can provide a speed increase of over 100,000× in comparison to SPICE-level simulations and allow interoperability with digital tools at the system-level. However, a key barrier to the expansion of system-level tools for analog circuits is the lack of confidence in system-level models implemented in SystemC AMS. Functional equivalence of single Laplace Transfer Function (LTF) system-level models to respective SPICE-level models was successfully demonstrated recently. However, this is clearly not sufficient, as the complex systems comprise multiple LTF modules. In this article, we go beyond single LTF models, i.e., we develop a novel graph-based methodology to formally check equivalence between complex system-level and SPICE-level representations of Single-Input Single-Output (SISO) linear analog circuits, such as High-Pass Filters (HPF). To achieve this, first, we introduce a canonical representation in the form of a Signal-Flow Graph (SFG), which is used to functionally map the two representations from separate modeling levels. This canonical representation consists of the input and output nodes and a single edge between them with an LTF as its weight. Second, we create an SFG representation with linear graph modeling for SPICE-level models, whereas for system-level models we extract an SFG from the behavioral description. We then transform the SFG representations into the canonical representation by utilizing three graph manipulation techniques, namely node removal, parallel edge unification, and reflexive edge elimination. This allows us to establish functional equivalence between complex system-level models and SPICE-level models. We demonstrate the applicability of the proposed methodology by successfully applying it to complex circuits.
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