相减W接触和局部互连协整(CLIC)

Fei Liu, B. Fletcher, E. Joseph, Yu Zhu, J. Gonsalves, W. Price, G. Fritz, S. Engelmann, A. Pyzyna, Zhen Zhang, C. Cabral, M. Guillorn
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引用次数: 3

摘要

研究了物理气相沉积(PVD)和化学气相沉积(CVD)制备的钨互连线的电阻率。探讨了沉积工艺和衬里膜堆的影响。结果表明,在线宽低至20nm,布线间距低至60nm的局部互连(LI)应用中,电阻率可接受。将CVD W触点和本地互连相结合的集成方案作为提供紧凑布线解决方案的一种手段,对工艺复杂性的影响最小。通过将本地互连与三极管集成,验证了布线概念。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Subtractive W contact and local interconnect co-integration (CLIC)
The resistivity of W interconnects deposited by physical vapor deposition (PVD) and chemical vapor deposition (CVD) is studied. The impacts of the deposition process and liner film stacks are explored. The results show acceptable resistivity for local interconnect (LI) applications with a linewidth down to 20nm and a wiring pitch down to 60nm. An integration scheme for combining a CVD W contact and local interconnect is explored as a means of providing a compact wiring solution with minimal impact on process complexity. The wiring concept is validated by integrating the local interconnects with trigate transistors.
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