迈向开放硬件:FPGA加速器的低成本设计、共享和部署平台

Q4 Engineering
Qian Zhao, M. Amagasaki, M. Iida, M. Kuga, T. Sueyoshi
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引用次数: 0

摘要

现场可编程门阵列(FPGA)是一种很有前途的技术,它通过将专用硬件作为协处理器来加速cpu的负载,从而实现高性能和低功耗的云计算。然而,由于硬件和软件协同设计的复杂性,开发基于fpga的系统是具有挑战性的。在本文中,我们提出了一个名为hCODE的平台来简化FPGA加速器的设计、共享和部署。首先,我们采用shell- ip设计模式来提高加速器设计的可重用性和可移植性。其次,我们实现了一个开放的加速器存储库,以在一个平台上连接硬件开发和软件开发。在hCODE平台上,硬件开发人员可以提供遵循hCODE规范的设计,这使得软件工程师可以轻松地搜索,下载和集成加速器到他们的应用程序中,而无需关心硬件细节。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost
Field-programmable gate array (FPGA) is a promising technology for the implementing of highperformance and power-efficient cloud computing by serving dedicated hardware as co-processor to accelerate loads on CPUs. However, developing an FPGA-based system is challenging because the complexity of the hardware and software co-design. In this paper, we propose a platform named hCODE to simplify the design, share, and deployment of FPGA accelerators. First, we adopt a shell-and-IP design pattern to improve the reusability and the portability of accelerator designs. Second, we implement an open accelerator repository to bridge hardware development and software development on one platform. On the hCODE platform, hardware developers can provide designs that follow hCODE specifications, which allowing software engineers to easily search, download, and integrate accelerators in their applications without caring about the hardware details.
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来源期刊
IPSJ Transactions on System LSI Design Methodology
IPSJ Transactions on System LSI Design Methodology Engineering-Electrical and Electronic Engineering
CiteScore
1.20
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0.00%
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