{"title":"ARM®Mali-T880移动GPU","authors":"Ian Bratt","doi":"10.1109/HOTCHIPS.2015.7477462","DOIUrl":null,"url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation. Mali-T880 Conclusion: Tile-based deferred rasterization with hierarchical tiling; Pipelined rendering, overlapping vertex processing and tiling from one frame, with fragment processing from the previous frame; Scalable from 1->16 shader cores, serving several markets; On-chip network enables ease of scalability; Integrated MMU and fixed-function Tiler; A pixel/cycle shader core serves as the fundamental building block, supporting simultaneous vertex and fragment shading; Designed from the ground up for power management; Multiple BW saving techniques, including Transaction Elimination, ARM Frame Buffer Compression, and Adaptive Scalable Texture Compression.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"60 1","pages":"1-27"},"PeriodicalIF":0.0000,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"The ARM® Mali-T880 Mobile GPU\",\"authors\":\"Ian Bratt\",\"doi\":\"10.1109/HOTCHIPS.2015.7477462\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article consists of a collection of slides from the author's conference presentation. Mali-T880 Conclusion: Tile-based deferred rasterization with hierarchical tiling; Pipelined rendering, overlapping vertex processing and tiling from one frame, with fragment processing from the previous frame; Scalable from 1->16 shader cores, serving several markets; On-chip network enables ease of scalability; Integrated MMU and fixed-function Tiler; A pixel/cycle shader core serves as the fundamental building block, supporting simultaneous vertex and fragment shading; Designed from the ground up for power management; Multiple BW saving techniques, including Transaction Elimination, ARM Frame Buffer Compression, and Adaptive Scalable Texture Compression.\",\"PeriodicalId\":6666,\"journal\":{\"name\":\"2015 IEEE Hot Chips 27 Symposium (HCS)\",\"volume\":\"60 1\",\"pages\":\"1-27\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE Hot Chips 27 Symposium (HCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HOTCHIPS.2015.7477462\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Hot Chips 27 Symposium (HCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOTCHIPS.2015.7477462","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This article consists of a collection of slides from the author's conference presentation. Mali-T880 Conclusion: Tile-based deferred rasterization with hierarchical tiling; Pipelined rendering, overlapping vertex processing and tiling from one frame, with fragment processing from the previous frame; Scalable from 1->16 shader cores, serving several markets; On-chip network enables ease of scalability; Integrated MMU and fixed-function Tiler; A pixel/cycle shader core serves as the fundamental building block, supporting simultaneous vertex and fragment shading; Designed from the ground up for power management; Multiple BW saving techniques, including Transaction Elimination, ARM Frame Buffer Compression, and Adaptive Scalable Texture Compression.