射频CMOS漏极和栅极电流噪声的紧凑建模

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI:10.1109/IEDM.2002.1175795

A. Scholten, L. Tiemeijer, R. Van Langevelde, R. Havens, V. Venezia, A. Zegers-van Duijnhoven, B. Neinhus, C. Jungemann, D.B.M. Klaasen

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引用次数: 30

摘要

提出了一种无需调整任何参数即可预测漏极和门极电流噪声的射频CMOS电路设计模型。此外，还揭示了(i)与雪崩倍增相关的噪声和(ii)漏电介质中直接隧穿栅极电流的散粒噪声的存在。

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Compact modeling of drain and gate current noise for RF CMOS

A model for RF CMOS circuit design is presented that is capable of predicting drain and gate current noise without adjusting any parameters. Additionally, the presence of (i) noise associated with avalanche multiplication, and (ii) shot noise of the direct-tunneling gate current in leaky dielectrics is revealed.

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来源期刊

Technical digest. International Electron Devices Meeting

CiteScore

4.50

自引率

0.00%

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