{"title":"级联匹配滤波器的混合信号设计","authors":"C. Su, Hung-Chi Lin, S. Jou","doi":"10.1109/ISCAS.1997.621573","DOIUrl":null,"url":null,"abstract":"This paper presents the design, implementation, and test of a mixed signal matched filter. It uses simple current mirrors to reduce the complexity of the crucial summation circuit. The circuit is small in size and regular in structure. They can be cascaded into filters of longer length. A 128-chip test chip has been implemented in a 2.5 mm/sup 2/ core by 0.8 /spl mu/m SPDM digital CMOS technology. The DC and AC measurement assert the feasibility of the design.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"36 1","pages":"2108-2111 vol.3"},"PeriodicalIF":0.0000,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Mixed signal design of cascadable matched filters\",\"authors\":\"C. Su, Hung-Chi Lin, S. Jou\",\"doi\":\"10.1109/ISCAS.1997.621573\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design, implementation, and test of a mixed signal matched filter. It uses simple current mirrors to reduce the complexity of the crucial summation circuit. The circuit is small in size and regular in structure. They can be cascaded into filters of longer length. A 128-chip test chip has been implemented in a 2.5 mm/sup 2/ core by 0.8 /spl mu/m SPDM digital CMOS technology. The DC and AC measurement assert the feasibility of the design.\",\"PeriodicalId\":68559,\"journal\":{\"name\":\"电路与系统学报\",\"volume\":\"36 1\",\"pages\":\"2108-2111 vol.3\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"电路与系统学报\",\"FirstCategoryId\":\"1093\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.1997.621573\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"电路与系统学报","FirstCategoryId":"1093","ListUrlMain":"https://doi.org/10.1109/ISCAS.1997.621573","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents the design, implementation, and test of a mixed signal matched filter. It uses simple current mirrors to reduce the complexity of the crucial summation circuit. The circuit is small in size and regular in structure. They can be cascaded into filters of longer length. A 128-chip test chip has been implemented in a 2.5 mm/sup 2/ core by 0.8 /spl mu/m SPDM digital CMOS technology. The DC and AC measurement assert the feasibility of the design.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
