Dong-chan Kim, W. Shin, Jaeduk Lee, Jinhyun Shin, Joon-hee Lee, S. Hur, Ihngee Baik, Yoocheol Shin, Changhyun Lee, J. Yoon, Heon-Guk Lee, Kwon-Soon Jo, Seungwook Choi, Byung-Kwan You, Jeong-Hyuk Choi, Donggun Park, Kinam Kim
{"title":"采用90nm闪存技术，容量为0.044 /spl mu/m/sup 2/ cell的2gb NAND闪存","authors":"Dong-chan Kim, W. Shin, Jaeduk Lee, Jinhyun Shin, Joon-hee Lee, S. Hur, Ihngee Baik, Yoocheol Shin, Changhyun Lee, J. Yoon, Heon-Guk Lee, Kwon-Soon Jo, Seungwook Choi, Byung-Kwan You, Jeong-Hyuk Choi, Donggun Park, Kinam Kim","doi":"10.1109/IEDM.2002.1175986","DOIUrl":null,"url":null,"abstract":"A manufacturable 2 Gb NAND flash memory with 0.044 /spl mu/m/sup 2/ cell size, which is the smallest cell size ever reported in semiconductor memory, is successfully developed with 90 nm NAND flash technology for high density file storage application. The three main key technology features of 90 nm NAND flash technology are advanced KrF lithography with off-axis illumination system equipped with a dipole aperture, reduced stack height of cell, and optimized gate reoxidation affecting tunnel oxide profile.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"160 1","pages":"919-922"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"A 2 Gb NAND flash memory with 0.044 /spl mu/m/sup 2/ cell size using 90 nm flash technology\",\"authors\":\"Dong-chan Kim, W. Shin, Jaeduk Lee, Jinhyun Shin, Joon-hee Lee, S. Hur, Ihngee Baik, Yoocheol Shin, Changhyun Lee, J. Yoon, Heon-Guk Lee, Kwon-Soon Jo, Seungwook Choi, Byung-Kwan You, Jeong-Hyuk Choi, Donggun Park, Kinam Kim\",\"doi\":\"10.1109/IEDM.2002.1175986\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A manufacturable 2 Gb NAND flash memory with 0.044 /spl mu/m/sup 2/ cell size, which is the smallest cell size ever reported in semiconductor memory, is successfully developed with 90 nm NAND flash technology for high density file storage application. The three main key technology features of 90 nm NAND flash technology are advanced KrF lithography with off-axis illumination system equipped with a dipole aperture, reduced stack height of cell, and optimized gate reoxidation affecting tunnel oxide profile.\",\"PeriodicalId\":74909,\"journal\":{\"name\":\"Technical digest. International Electron Devices Meeting\",\"volume\":\"160 1\",\"pages\":\"919-922\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Technical digest. International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2002.1175986\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Technical digest. International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2002.1175986","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 2 Gb NAND flash memory with 0.044 /spl mu/m/sup 2/ cell size using 90 nm flash technology
A manufacturable 2 Gb NAND flash memory with 0.044 /spl mu/m/sup 2/ cell size, which is the smallest cell size ever reported in semiconductor memory, is successfully developed with 90 nm NAND flash technology for high density file storage application. The three main key technology features of 90 nm NAND flash technology are advanced KrF lithography with off-axis illumination system equipped with a dipole aperture, reduced stack height of cell, and optimized gate reoxidation affecting tunnel oxide profile.
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