Yunsup Lee, B. Zimmer, Andrew Waterman, A. Puggelli, Jaehwa Kwak, R. Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, P. Chiu, Henry Cook, Rimas Avizienis, B. Richards, E. Alon, B. Nikolić, K. Asanović
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Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking
This article consists of a collection of slides from the authors' conference presentation. The topics discussed included: Motivation/Raven Project Goals; On-Chip Switched Capacitor DC-DC Converters; Raven3 Chip Architecture; Raven3 Implementation; Raven3 Evaluation; and RISC-V Chip Building at UC Berkeley.