从器件到电路:模拟5nm纳米片的性能

2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) Pub Date : 2019-09-01 DOI:10.1109/SISPAD.2019.8870357

A. Brown, Liping Wang, P. Asenov, F. Klüpfel, B. Cheng, S. Martinie, O. Rozeau, S. Barraud, J. Barbe, C. Millar, J. Lorenz

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引用次数: 0

摘要

提出了一种利用5nm堆叠纳米线进行设计-技术协同优化的仿真流程。关键过程参数变化对基准电路行为的影响通过使用可变感知紧凑模型进行检查，考虑全局和局部可变性。

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From devices to circuits: modelling the performance of 5nm nanosheets

A simulation flow for design-technology co-optimisation using 5nm stacked nanowires is presented. The effect of variation in key process parameters on the behaviour of benchmark circuits is examined through the use of variability-aware compact models, accounting for both global and local variability.

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2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

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