一种具有轨对轨输入/输出摆幅的0.5 V AB类准FGMOS伪全差分CMOS运放

2011 Fourth International Conference on Modeling, Simulation and Applied Optimization Pub Date : 2011-04-19 DOI:10.1109/ICMSAO.2011.5775556

Thawatchai Thongleam, A. Suadet, Arnon Kanjanop, Pratchayaporn Singhanath, Buncha Hirunsing, Weerasak Chuenta, V. Kasemsuwan

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引用次数: 1

摘要

本文提出了一种具有轨对轨输入/输出摆幅的0.5 V伪全差分CMOS运放。该电路是基于AB类输入输出级设计的。在设计中，采用了准FGMOS晶体管。该放大器采用0.18 μm CMOS工艺设计，仿真结果显示出轨间输入和输出振荡。开环增益和增益带宽积分别为73.3 dB和12.6 MHz。CMRR为73.2 dB (1khz)，功耗为27.9 μW。

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A 0.5 V class AB quasi FGMOS pseudo fully differential CMOS op-amp with rail-to-rail input/output swing

This paper presents a 0.5 V pseudo fully differential CMOS op-amp with rail-to-rail input/output swing. The circuit is designed based on class AB input and output stages. In the design, quasi FGMOS transistors are employed. The proposed amplifier is designed using 0.18 μm CMOS technology, and the simulation results show rail-to-rail input and output swings. The open-loop gain and gain-bandwidth product show 73.3 dB and 12.6 MHz. The CMRR is 73.2 dB (at 1 kHz) and the power consumption is 27.9 μW.

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2011 Fourth International Conference on Modeling, Simulation and Applied Optimization

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