氮化硅层内嵌硅纳米晶电荷捕获存储器的模拟

2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI:10.1109/SNW.2012.6243351

Yahua Peng, Xiaoyan Liu, G. Du, Yan Yang, Jinfeng Kang

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引用次数: 0

摘要

提出了一种评价纳米晶体加入电荷阱层的CTM性能的模拟方法，并研究了偏压、电荷阱分布、纳米晶体尺寸、温度和栅极介电层厚度对程序/擦除/保留特性的影响。它可以为纳米晶体CTM的设计提供一个有用的工具。

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Simulation of charge trapping memory with silicon nanocrystals embedded in silicon nitride layer

A simulation method for evaluating the performance of CTM with incorporating nanocrystals into the charge trap layer is presented and the effects of bias voltage, charge trap distribution, nanocrystal size, temperature and gate dielectric layer's thickness on program/erase/retention characteristic are studied. It can be a useful tool for designing nanocrystals based CTM.

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2012 IEEE Silicon Nanoelectronics Workshop (SNW)

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