FPGA-based test bed for design and evaluation of low-power FIR-filter hardware accelerators

Finite impulse response (FIR) filters are often used for processing audio, communication and other signals. Truncated-matrix multipliers offer reduced area, power and delay at the expense of increased computational error. This paper describes a test bed for low-power FIR-filter hardware accelerators that use truncated-matrix multipliers. It accepts analog input signals, filters them in real-time using an inexpensive field-programmable gate array (FPGA) development board, and produces analog outputs. The input is simultaneously processed using truncated-matrix multipliers and standard multipliers for comparison. Parameters such as filter coefficients, the number of unformed columns and the error correction method can be changed on the fly. The test bed enables real-time testing at the systems-integration level using real analog inputs and outputs.