K. Yamazaki, Yoshihiro Nakajima, T. Hatano, A. Miyazaki
{"title":"Lagopus FPGA——用于高性能软件SDN交换机的可重新编程数据平面","authors":"K. Yamazaki, Yoshihiro Nakajima, T. Hatano, A. Miyazaki","doi":"10.1109/HOTCHIPS.2015.7477471","DOIUrl":null,"url":null,"abstract":"This article consists of one slide from the authors' conference presentation. Some of the topics discussed include: What is SDN and why?; What is Lagopus vSwitch?; Packet processing on multi-core CPUs; Issues of CPU centralized processing; Designing concept and architecture; FPGA flow classification & dispatch empowered by SDNet and flow director; Performance vs. Power Dissipation; and Demonstration.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"23 1 1","pages":"1-1"},"PeriodicalIF":0.0000,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Lagopus FPGA -- A reprogrammable data plane for high-performance software SDN switches\",\"authors\":\"K. Yamazaki, Yoshihiro Nakajima, T. Hatano, A. Miyazaki\",\"doi\":\"10.1109/HOTCHIPS.2015.7477471\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article consists of one slide from the authors' conference presentation. Some of the topics discussed include: What is SDN and why?; What is Lagopus vSwitch?; Packet processing on multi-core CPUs; Issues of CPU centralized processing; Designing concept and architecture; FPGA flow classification & dispatch empowered by SDNet and flow director; Performance vs. Power Dissipation; and Demonstration.\",\"PeriodicalId\":6666,\"journal\":{\"name\":\"2015 IEEE Hot Chips 27 Symposium (HCS)\",\"volume\":\"23 1 1\",\"pages\":\"1-1\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE Hot Chips 27 Symposium (HCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HOTCHIPS.2015.7477471\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Hot Chips 27 Symposium (HCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOTCHIPS.2015.7477471","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Lagopus FPGA -- A reprogrammable data plane for high-performance software SDN switches
This article consists of one slide from the authors' conference presentation. Some of the topics discussed include: What is SDN and why?; What is Lagopus vSwitch?; Packet processing on multi-core CPUs; Issues of CPU centralized processing; Designing concept and architecture; FPGA flow classification & dispatch empowered by SDNet and flow director; Performance vs. Power Dissipation; and Demonstration.