Avalanche Robustness of 1.2kV SiC MOSFET with Integrated Junction-Barrier-Schottky Diode and Gate Leakage Current Analysis

In this work, 1.2kV SiC MOSFET integrated Junction-Barrier-Schottky diode (JMOS) is fabricated. The Schottky width is 2μm. The static characteristic of the JMOS is evaluated at room and elevated temperature. The single pulse avalanche robustness under Vgs= −5V is studied. Moreover, excessive gate leakage current is observed during the avalanche. The mechanism of gate leakage current is studied by simulation. The high impact ionization and high temperature in JFET region causes high gate leakage current. The transfer characteristic after each UIS test is monitored to confirm ionized holes inject into gate oxide during the avalanche.