高效的低功耗总线架构

电路与系统学报 Pub Date : 1997-06-09 DOI:10.1109/ISCAS.1997.621512

A. Rjoub, S. Nikolaidis, O. Koufopavlou, T. Stouraitis

{"title":"高效的低功耗总线架构","authors":"A. Rjoub, S. Nikolaidis, O. Koufopavlou, T. Stouraitis","doi":"10.1109/ISCAS.1997.621512","DOIUrl":null,"url":null,"abstract":"In this paper a new low power bus architecture based on the reduced voltage swing technique, is proposed. A driver circuit and a receiver are designed using strictly simple design principles and conventional CMOS technology. A considerable reduction in power consumption is achieved. The influence of the swing level on the time performance is also examined. The same architecture with a new repeater circuit is used, for driving internal long interconnection lines and similar results are obtained.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"An efficient low-power bus architecture\",\"authors\":\"A. Rjoub, S. Nikolaidis, O. Koufopavlou, T. Stouraitis\",\"doi\":\"10.1109/ISCAS.1997.621512\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper a new low power bus architecture based on the reduced voltage swing technique, is proposed. A driver circuit and a receiver are designed using strictly simple design principles and conventional CMOS technology. A considerable reduction in power consumption is achieved. The influence of the swing level on the time performance is also examined. The same architecture with a new repeater circuit is used, for driving internal long interconnection lines and similar results are obtained.\",\"PeriodicalId\":68559,\"journal\":{\"name\":\"电路与系统学报\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"电路与系统学报\",\"FirstCategoryId\":\"1093\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.1997.621512\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"电路与系统学报","FirstCategoryId":"1093","ListUrlMain":"https://doi.org/10.1109/ISCAS.1997.621512","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 12

摘要

本文提出了一种基于降低电压摆幅技术的新型低功耗总线结构。采用严格简单的设计原则和传统的CMOS技术设计了驱动电路和接收器。大大降低了能耗。研究了摆动水平对时间性能的影响。采用相同的结构和一种新的中继电路，驱动内部长互连线，得到了类似的结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An efficient low-power bus architecture

In this paper a new low power bus architecture based on the reduced voltage swing technique, is proposed. A driver circuit and a receiver are designed using strictly simple design principles and conventional CMOS technology. A considerable reduction in power consumption is achieved. The influence of the swing level on the time performance is also examined. The same architecture with a new repeater circuit is used, for driving internal long interconnection lines and similar results are obtained.

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来源期刊

电路与系统学报

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发文量

2463