2D vs 3D集成:未来移动MPSoC平台的架构-技术协同设计

2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI:10.1109/IITC.2014.6831839

Prashant Agrawal, D. Milojevic, P. Raghavan, F. Catthoor, L. Van der Perre, E. Beyne, R. Varadarajan

{"title":"2D vs 3D集成:未来移动MPSoC平台的架构-技术协同设计","authors":"Prashant Agrawal, D. Milojevic, P. Raghavan, F. Catthoor, L. Van der Perre, E. Beyne, R. Varadarajan","doi":"10.1109/IITC.2014.6831839","DOIUrl":null,"url":null,"abstract":"3D stacked ICs (3D-SIC) are viable alternatives to overcome limitations faced by mobile MPSoC platforms in 2D designs. In this paper, we evaluate 2D-ICs and 3D-SICs (memory-on-logic) at system architecture level for a complex MPSoC platform instantiated for wireless PHY processing (WLAN, LTE). For a 10-core heterogeneous MPSoC instantiation, we compare its implementations as 2D-IC and 3D-SIC (based on Cu-Cu bonding), and for two different level-1 data memory organization and communication bus structure. We also analyse impact of system level choices (memory organization, communication structure) for both 2D and 3D interconnects.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"2 1","pages":"381-384"},"PeriodicalIF":0.0000,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"2D vs 3D integration: Architecture-technology co-design for future mobile MPSoC platforms\",\"authors\":\"Prashant Agrawal, D. Milojevic, P. Raghavan, F. Catthoor, L. Van der Perre, E. Beyne, R. Varadarajan\",\"doi\":\"10.1109/IITC.2014.6831839\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"3D stacked ICs (3D-SIC) are viable alternatives to overcome limitations faced by mobile MPSoC platforms in 2D designs. In this paper, we evaluate 2D-ICs and 3D-SICs (memory-on-logic) at system architecture level for a complex MPSoC platform instantiated for wireless PHY processing (WLAN, LTE). For a 10-core heterogeneous MPSoC instantiation, we compare its implementations as 2D-IC and 3D-SIC (based on Cu-Cu bonding), and for two different level-1 data memory organization and communication bus structure. We also analyse impact of system level choices (memory organization, communication structure) for both 2D and 3D interconnects.\",\"PeriodicalId\":6823,\"journal\":{\"name\":\"2021 IEEE International Interconnect Technology Conference (IITC)\",\"volume\":\"2 1\",\"pages\":\"381-384\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-05-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE International Interconnect Technology Conference (IITC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC.2014.6831839\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Interconnect Technology Conference (IITC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2014.6831839","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

3D堆叠ic (3D- sic)是克服移动MPSoC平台在2D设计中面临的局限性的可行替代方案。在本文中，我们在系统架构级别评估了用于无线PHY处理(WLAN, LTE)实例化的复杂MPSoC平台的2d - ic和3d - sic(逻辑上的内存)。对于一个10核异构MPSoC实例，我们比较了其实现为2D-IC和3D-SIC(基于Cu-Cu键合)，以及两种不同的一级数据存储器组织和通信总线结构。我们还分析了系统级选择(存储器组织，通信结构)对2D和3D互连的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

2D vs 3D integration: Architecture-technology co-design for future mobile MPSoC platforms

3D stacked ICs (3D-SIC) are viable alternatives to overcome limitations faced by mobile MPSoC platforms in 2D designs. In this paper, we evaluate 2D-ICs and 3D-SICs (memory-on-logic) at system architecture level for a complex MPSoC platform instantiated for wireless PHY processing (WLAN, LTE). For a 10-core heterogeneous MPSoC instantiation, we compare its implementations as 2D-IC and 3D-SIC (based on Cu-Cu bonding), and for two different level-1 data memory organization and communication bus structure. We also analyse impact of system level choices (memory organization, communication structure) for both 2D and 3D interconnects.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2021 IEEE International Interconnect Technology Conference (IITC)

自引率

0.00%

发文量