2D vs 3D集成:未来移动MPSoC平台的架构-技术协同设计

2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI:10.1109/IITC.2014.6831839

Prashant Agrawal, D. Milojevic, P. Raghavan, F. Catthoor, L. Van der Perre, E. Beyne, R. Varadarajan

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引用次数: 2

摘要

3D堆叠ic (3D- sic)是克服移动MPSoC平台在2D设计中面临的局限性的可行替代方案。在本文中，我们在系统架构级别评估了用于无线PHY处理(WLAN, LTE)实例化的复杂MPSoC平台的2d - ic和3d - sic(逻辑上的内存)。对于一个10核异构MPSoC实例，我们比较了其实现为2D-IC和3D-SIC(基于Cu-Cu键合)，以及两种不同的一级数据存储器组织和通信总线结构。我们还分析了系统级选择(存储器组织，通信结构)对2D和3D互连的影响。

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2D vs 3D integration: Architecture-technology co-design for future mobile MPSoC platforms

3D stacked ICs (3D-SIC) are viable alternatives to overcome limitations faced by mobile MPSoC platforms in 2D designs. In this paper, we evaluate 2D-ICs and 3D-SICs (memory-on-logic) at system architecture level for a complex MPSoC platform instantiated for wireless PHY processing (WLAN, LTE). For a 10-core heterogeneous MPSoC instantiation, we compare its implementations as 2D-IC and 3D-SIC (based on Cu-Cu bonding), and for two different level-1 data memory organization and communication bus structure. We also analyse impact of system level choices (memory organization, communication structure) for both 2D and 3D interconnects.

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2021 IEEE International Interconnect Technology Conference (IITC)

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