A Low Power Binary to Excess-1 CodeConverter Using GDI Technique

In this work a binary to excess-1 code converter is achieved by using GDI technique for the faster acceleration of the final addition in a hybrid adder. It is applied to the faster column compression multiplication using a combination of two design techniques: partition of the partial products into two parts for independent parallel column compression and acceleration of the addition using hybrid adder. The performance of the proposed design is compared with CMOS technology by evaluating the delay, power and transistor count with 180nm process technologies on Tanner EDA tools. The results show the proposed design is significantly lower than CMOS technology.