一种用于高性能流处理的新型处理器架构

2015 IEEE Hot Chips 27 Symposium (HCS) Pub Date : 2006-08-01 DOI:10.1109/HOTCHIPS.2006.7477868

J. V. Lunteren

{"title":"一种用于高性能流处理的新型处理器架构","authors":"J. V. Lunteren","doi":"10.1109/HOTCHIPS.2006.7477868","DOIUrl":null,"url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation on a novel processor architecture for high performance stream processing. Some of the specific topics discussed include: an introduction to the technology and applications supported; high-level concept design; programmable state machine; novel processor technologies; instructure cache ad prefetch; and experimental results for testing the performance output.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"17 1","pages":"1-24"},"PeriodicalIF":0.0000,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A novel processor architecture for high-performance stream processing\",\"authors\":\"J. V. Lunteren\",\"doi\":\"10.1109/HOTCHIPS.2006.7477868\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article consists of a collection of slides from the author's conference presentation on a novel processor architecture for high performance stream processing. Some of the specific topics discussed include: an introduction to the technology and applications supported; high-level concept design; programmable state machine; novel processor technologies; instructure cache ad prefetch; and experimental results for testing the performance output.\",\"PeriodicalId\":6666,\"journal\":{\"name\":\"2015 IEEE Hot Chips 27 Symposium (HCS)\",\"volume\":\"17 1\",\"pages\":\"1-24\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE Hot Chips 27 Symposium (HCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HOTCHIPS.2006.7477868\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Hot Chips 27 Symposium (HCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOTCHIPS.2006.7477868","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

本文由作者在会议上关于一种用于高性能流处理的新型处理器架构的演讲中的幻灯片组成。讨论的一些具体主题包括:对所支持的技术和应用程序的介绍;高级概念设计;可编程状态机;新颖的处理器技术;基础架构缓存AD预取;并将实验结果用于测试性能输出。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A novel processor architecture for high-performance stream processing

This article consists of a collection of slides from the author's conference presentation on a novel processor architecture for high performance stream processing. Some of the specific topics discussed include: an introduction to the technology and applications supported; high-level concept design; programmable state machine; novel processor technologies; instructure cache ad prefetch; and experimental results for testing the performance output.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2015 IEEE Hot Chips 27 Symposium (HCS)

自引率

0.00%

发文量