活动分析:审查不同的解决方案，以开发可靠和高性能的设计

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI:10.1109/IOLTS.2016.7604670

F. Cacho, A. Benhassain, S. Mhira, A. Sivadasan, V. Huard, P. Cathelin, V. Knopik, A. Jain, C. Parthasarathy, L. Anghel

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引用次数: 0

摘要

先进CMOS节点的可靠性正变得非常具有挑战性。高性能和可靠性需求之间的权衡不能再通过粗略的额外利润来解决。这将导致过度设计和严重的性能和面积损失。对任务轮廓的精细分析是准确评估老化的途径。对方法和结果进行了广泛的回顾，它们适用于数字，模拟和射频/毫米波电路。给出了一组重要的实验结果，并与仿真结果进行了比较。本文强调了活动分析或工作负载与老化引起的性能下降之间的相关性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Activity profiling: Review of different solutions to develop reliable and performant design

Reliability for advanced CMOS nodes is becoming very challenging. The trade-off between high performance and reliability requirement can no longer be addressed by rough extra-margin. It would results in an overdesign and strong penalty of performance and area. A fine-grain analysis of mission profile is the path toward accurate assessment of ageing. A wide review of methodologies and results are presented, they are applied to digital, analog and RF/mmW circuits. Important set of experimental results are shown and compared to simulation. This paper highlights the correlation between activity profiling or workload and degradation performance induced by ageing.

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2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)

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