Guilian Gao, L. Mirkarimi, G. Fountain, Liang Wang, C. Uzoh, Thomas Workman, Gabe Guevara, Chandrasekhar Mandalapu, Bongsub Lee, R. Katkar
{"title":"缩放封装互连低于20µm间距与混合键合","authors":"Guilian Gao, L. Mirkarimi, G. Fountain, Liang Wang, C. Uzoh, Thomas Workman, Gabe Guevara, Chandrasekhar Mandalapu, Bongsub Lee, R. Katkar","doi":"10.1109/ECTC.2018.00055","DOIUrl":null,"url":null,"abstract":"The low-temperature direct bond interconnect commonly referred to as hybrid bonding technology is a promising solution for achieving an interconnect pitch smaller than 40µm. Wafer-to-wafer (W2W) direct bond interconnect technology has been in high volume manufacturing for several years. This paper presents the latest development for extending this technology from W2W to die-to-wafer (D2W) and die-to-die (D2D) applications. Daisy chain die with direct bond interconnect layers on either one or both surfaces are designed with a similar size to a high bandwidth dynamic random access memory (HBM DRAM) die, 7.96 mm x 11.96 mm. The longest daisy chain structure has 31,356 links and covers an active area of 5.36mm x 9.36mm. The bonding pitch ranges from 10 to 40 µm with a pad diameter of either 5 or 10 µm. The paper addresses the critical issues in bringing direct bond interconnect into a manufacturing environment with a D2W or D2D assembly flow while sharing the latest results. The assembly topics addressed here include extension of CMP to 10 µm pads, dicing, surface preparation for the direct bonding in a pick and place tool. The dies bond to a full-thickness host wafer integrated with a mating daisy chain to demonstrate electrical connectivity. Bond quality is characterized with C-mode scanning acoustic microscopy (CSAM), electrical resistance measurement, and cross-section microscopy analysis. Electrical test yield as high as 92% on the full daisy chain is achieved. Bonded parts have showed superior reliability in the JEDEC standard thermal cycling and high temperature storage testing.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"125 1","pages":"314-322"},"PeriodicalIF":0.0000,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":"{\"title\":\"Scaling Package Interconnects Below 20µm Pitch with Hybrid Bonding\",\"authors\":\"Guilian Gao, L. Mirkarimi, G. Fountain, Liang Wang, C. Uzoh, Thomas Workman, Gabe Guevara, Chandrasekhar Mandalapu, Bongsub Lee, R. Katkar\",\"doi\":\"10.1109/ECTC.2018.00055\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The low-temperature direct bond interconnect commonly referred to as hybrid bonding technology is a promising solution for achieving an interconnect pitch smaller than 40µm. Wafer-to-wafer (W2W) direct bond interconnect technology has been in high volume manufacturing for several years. This paper presents the latest development for extending this technology from W2W to die-to-wafer (D2W) and die-to-die (D2D) applications. Daisy chain die with direct bond interconnect layers on either one or both surfaces are designed with a similar size to a high bandwidth dynamic random access memory (HBM DRAM) die, 7.96 mm x 11.96 mm. The longest daisy chain structure has 31,356 links and covers an active area of 5.36mm x 9.36mm. The bonding pitch ranges from 10 to 40 µm with a pad diameter of either 5 or 10 µm. The paper addresses the critical issues in bringing direct bond interconnect into a manufacturing environment with a D2W or D2D assembly flow while sharing the latest results. The assembly topics addressed here include extension of CMP to 10 µm pads, dicing, surface preparation for the direct bonding in a pick and place tool. The dies bond to a full-thickness host wafer integrated with a mating daisy chain to demonstrate electrical connectivity. Bond quality is characterized with C-mode scanning acoustic microscopy (CSAM), electrical resistance measurement, and cross-section microscopy analysis. Electrical test yield as high as 92% on the full daisy chain is achieved. Bonded parts have showed superior reliability in the JEDEC standard thermal cycling and high temperature storage testing.\",\"PeriodicalId\":6555,\"journal\":{\"name\":\"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)\",\"volume\":\"125 1\",\"pages\":\"314-322\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"25\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECTC.2018.00055\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2018.00055","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 25
摘要
低温直接键合互连通常被称为混合键合技术,是实现互连间距小于40µm的有前途的解决方案。晶圆对晶圆(W2W)直接键合互连技术已经大批量生产了好几年。本文介绍了将该技术从W2W扩展到晶圆(D2W)和晶圆(D2D)应用的最新进展。在一个或两个表面上具有直接键合互连层的菊花链芯片的设计尺寸与高带宽动态随机存取存储器(HBM DRAM)芯片相似,为7.96 mm x 11.96 mm。最长的菊花链结构有31,356个链接,覆盖5.36mm x 9.36mm的活动面积。键合间距范围为10 ~ 40 μ m,焊盘直径为5或10 μ m。本文讨论了将直接键合互连引入具有D2W或D2D装配流程的制造环境中的关键问题,同时分享了最新成果。这里讨论的组装主题包括将CMP扩展到10 μ m焊盘,切割,在拾取和放置工具中直接粘合的表面准备。模具结合到一个全厚度的主晶圆集成配合菊花链,以证明电气连接。用c型扫描声学显微镜(CSAM)、电阻测量和截面显微镜分析来表征键合质量。在全雏菊链上实现了高达92%的电气测试良率。结合件在JEDEC标准热循环和高温储存试验中表现出优异的可靠性。
Scaling Package Interconnects Below 20µm Pitch with Hybrid Bonding
The low-temperature direct bond interconnect commonly referred to as hybrid bonding technology is a promising solution for achieving an interconnect pitch smaller than 40µm. Wafer-to-wafer (W2W) direct bond interconnect technology has been in high volume manufacturing for several years. This paper presents the latest development for extending this technology from W2W to die-to-wafer (D2W) and die-to-die (D2D) applications. Daisy chain die with direct bond interconnect layers on either one or both surfaces are designed with a similar size to a high bandwidth dynamic random access memory (HBM DRAM) die, 7.96 mm x 11.96 mm. The longest daisy chain structure has 31,356 links and covers an active area of 5.36mm x 9.36mm. The bonding pitch ranges from 10 to 40 µm with a pad diameter of either 5 or 10 µm. The paper addresses the critical issues in bringing direct bond interconnect into a manufacturing environment with a D2W or D2D assembly flow while sharing the latest results. The assembly topics addressed here include extension of CMP to 10 µm pads, dicing, surface preparation for the direct bonding in a pick and place tool. The dies bond to a full-thickness host wafer integrated with a mating daisy chain to demonstrate electrical connectivity. Bond quality is characterized with C-mode scanning acoustic microscopy (CSAM), electrical resistance measurement, and cross-section microscopy analysis. Electrical test yield as high as 92% on the full daisy chain is achieved. Bonded parts have showed superior reliability in the JEDEC standard thermal cycling and high temperature storage testing.