{"title":"一种用于最小和模拟迭代解码器的低电压电流模式最大赢家通吃电路","authors":"S. Hemati, A. Banihashemi","doi":"10.1109/ICECS.2003.1301962","DOIUrl":null,"url":null,"abstract":"A new current-mode maximum winner-take-all (max WTA) circuit is presented. Inputs and output of the circuit are high swing, and voltage requirements for the inputs and the output are very low and just about V/sub eff/ (V/sub sat/) and 2 V/sub eff/ (2 V/sub sat/), respectively. Because of the cascode configuration, the proposed circuit shows very good precision even for short channel MOSFETs. Simulation results based on 0.13 /spl mu/m UMC CMOS technology are also presented. These results demonstrate the high-precision and low-voltage requirement of the circuit, which makes it a good choice for low-voltage min-sum analog iterative decoders and other soft computing applications.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"57 10 1","pages":"4-7 Vol.1"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A current mode maximum winner-take-all circuit with low voltage requirement for min-sum analog iterative decoders\",\"authors\":\"S. Hemati, A. Banihashemi\",\"doi\":\"10.1109/ICECS.2003.1301962\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new current-mode maximum winner-take-all (max WTA) circuit is presented. Inputs and output of the circuit are high swing, and voltage requirements for the inputs and the output are very low and just about V/sub eff/ (V/sub sat/) and 2 V/sub eff/ (2 V/sub sat/), respectively. Because of the cascode configuration, the proposed circuit shows very good precision even for short channel MOSFETs. Simulation results based on 0.13 /spl mu/m UMC CMOS technology are also presented. These results demonstrate the high-precision and low-voltage requirement of the circuit, which makes it a good choice for low-voltage min-sum analog iterative decoders and other soft computing applications.\",\"PeriodicalId\":36912,\"journal\":{\"name\":\"Czas Kultury\",\"volume\":\"57 10 1\",\"pages\":\"4-7 Vol.1\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-12-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Czas Kultury\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2003.1301962\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"Arts and Humanities\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Czas Kultury","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2003.1301962","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"Arts and Humanities","Score":null,"Total":0}
A current mode maximum winner-take-all circuit with low voltage requirement for min-sum analog iterative decoders
A new current-mode maximum winner-take-all (max WTA) circuit is presented. Inputs and output of the circuit are high swing, and voltage requirements for the inputs and the output are very low and just about V/sub eff/ (V/sub sat/) and 2 V/sub eff/ (2 V/sub sat/), respectively. Because of the cascode configuration, the proposed circuit shows very good precision even for short channel MOSFETs. Simulation results based on 0.13 /spl mu/m UMC CMOS technology are also presented. These results demonstrate the high-precision and low-voltage requirement of the circuit, which makes it a good choice for low-voltage min-sum analog iterative decoders and other soft computing applications.
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