High Density Package Design Platform and Assembly Design Kit

With the miniaturization of integrated circuit technology and process, chips are getting smaller and smaller, and thus it results in fan-out packaging with RDL process was derived to extend the ball grid array design space. The applicable range of RDL now includes products in the fields of Networking, HPC, AI and even SiPh. And the new package types comprised of the RDL process include e-WLB, chip first FOCoS, chip last FOCoS, FO-PoP and 2.5D IC etc. The total pin count in FOCoS packaging can be more than ten times than that the pin counts in a large FCBGA packaging; the FOCoS package layout density can reach tens or even hundreds of times than FCBGA. High density and complex connectivity in FOCoS cause more difficult using traditional EDA tool for packaging design. In addition, the RDL process manufacturing equipment is different from that for traditional packaging substrate and it is more like the foundry process, so it is required to consider design rule check and LVS check flow compatible to IC design flow except for the package layout. It is necessary to have different methods and tools from that in the past to complete a reliable design. In this paper, there is an introduction about the new design flow and platform for high density package design and it describes the new design platform could overcome the difficulties of layout on high-density packages such as FOCoS. And then talking about FOCoS Assembly Design Kit (ADK) to provide to the IC or system designers, especially the new design rule checking tools and procedure, as well as example about how DRC tools plays an important role in RDL process improvement and design. In addition to checking the design rule for the layout, verifying the interconnections between the components in the package after design is very important to FOCoS packaging which is generally used in multiple dice integration such as homogeneous and heterogeneous integration design.