基于范德华异质结构的亚飞焦耳能量消耗存储器

Chip Pub Date : 2022-06-01 DOI:10.1016/j.chip.2022.100014
Zi-Jia Su , Zi-Hao Xuan , Jing Liu , Yi Kang , Chun-Sen Liu , Cheng-Jie Zuo
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引用次数: 3

摘要

内存计算在每个存储单元内就地进行计算,其主要功耗来自数据写入和擦除。内存计算的能量效率的进一步改进需要具有亚飞焦耳能量消耗的存储设备。基于二维(2D)材料异质结构的浮栅存储器件具有非易失性、多比特存储和低运行能量等突出特点,适合应用于内存计算芯片。本文报道了一种基于WSe2/h-BN/多层石墨烯/h-BN异质结构的浮栅存储器件,其每次操作的编程/擦除能耗在亚飞焦耳(0.6 fJ),读取功耗在几十飞瓦特(60 fW)范围内。我们展示了由WSe2/h-BN/多层石墨烯/h-BN异质结构浮栅存储器件组成的Hopfield神经网络,该网络可以从错误的图案中回忆出原始图案。这些结果为内存计算系统的未来紧凑和节能硬件的发展提供了启示。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Sub-femto-Joule energy consumption memory device based on van der Waals heterostructure for in-memory computing

In-memory computing has carried out calculations in situ within each memory unit and its main power consumption comes from data writing and erasing. Further improvements in the energy efficiency of in-memory computing require memory devices with sub-femto-Joule energy consumption. Floating gate memory devices based on two-dimensional (2D) material heterostructures have outstanding characteristics such as non-volatility, multi-bit storage, and low operation energy, suitable for application in in-memory computing chips. Here, we report a floating gate memory device based on a WSe2/h-BN/Multilayer-graphene/h-BN heterostructure, the energy consumption of which is in sub-femto Joule (0.6 fJ) per operation for program/erase, and the read power consumption is in the tens of femto Watt (60 fW) range. We show a Hopfield neural network composed of WSe2/h-BN/Multilayer-graphene/h-BN heterostructure floating gate memory devices, which can recall the original patterns from incorrect patterns. These results shed light on the development of future compact and energy-efficient hardware for in-memory computing systems.

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CiteScore
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