高效sigma-delta转换器的十进制结构概述:趋势、设计问题和实际解决方案

G. Salgado, G. Jovanovic-Dolecek, J. M. Rosa
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引用次数: 4

摘要

由于梳状滤波器的简单性,经典的抽取结构通常在第一阶段使用梳状滤波器。然而,梳状滤波器不能满足最先进的Sigma-Delta (ΣΔ)模数转换器(adc)的高性能要求。一些可能的解决方案是基于梳状结构,它具有功率和面积效率,并具有改进的幅度特性。基于梳状滤波器设计的主要问题是:功率和面积效率,高混叠抑制和近似平通带特性,同时还要考虑高值的抽取因子。在本文中,我们首先回顾了ΣΔ adc的新趋势和对抽取块设计的要求。接下来,我们将回顾功率和面积效率结构。本文综述了改善梳状滤波器混叠抑制性能的方法,以及对梳状滤波器通带下垂的补偿方法,以及同时改善混叠抑制和通带下垂的策略。最后回顾了多率抽取结构。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An overview of decimator structures for efficient sigma-delta converters: Trends, design issues and practical solutions
Classical decimation structures usually use comb filters at first stage due to the simplicity of comb filters. However, comb filters cannot satisfy high performance demands of state-of-the-art Sigma-Delta (ΣΔ) analog-digital converters (ADCs). Some possible solutions are comb based structures which are power and area efficient and posses an improved magnitude characteristic. The principal issues in the comb-based filter design are: power and area efficiency, high alias rejection and approximately flat passband characteristic, considering also high values of the decimation factors. In this paper we first review the new trends in ΣΔ ADCs and demands for the decimation block design. Next we review power and area efficient structures. The methods to improve the alias rejection of comb filters, as well as the methods for the compensation for the comb passband droop, and those strategies which simultaneously improve the alias rejection and the passband droop are reviewed in the following. Finally we review the multirate decimation structures.
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