一种用于低内压ULSI系统的新型BiCMOS增加全摆幅变换器

Ching-Sung Wang, Shih-Yi Yuan, Ke-Horng Chen, S. Kuo
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引用次数: 0

摘要

本文提出了一种适用于低电压/低功耗超大型集成电路(ULSI)系统的新型BiCMOS增强型全摆幅逆变器(IFSI)和新型BiCMOS增强型全摆幅缓冲器(IFSB)。这些电路可以在低内部电压(V/sub / int/)下工作,并且具有低输入信号摆幅。只要V/sub int/>|V/sub t/|(假设V/sub tn/=-V/sub tp/),电路就能正常工作。所提出的BiCMOS IFSC电路适用于高速操作。当电容负载大于0.6 pf时;在相同的电路设计参数下,不同内部电压下的传播延迟和延迟功率积都优于以往的电路。我们还建立了Kr=Kn/Kp比值与电路面积的关系。这可以避免在电路尺寸操作的试错步骤,以减少功耗。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A new BiCMOS increased full swing converter for low-internal-voltage ULSI systems
In this paper a new BiCMOS increased full swing inverter (IFSI) and a new BiCMOS increased full swing buffer (IFSB) for low voltage/low power ULSI (Ultra Large Scale Integration) systems are proposed. These circuits can operate at low internal voltage (V/sub int/) and have low input signal swing. As long as V/sub int/>|V/sub t/| (assuming V/sub tn/=-V/sub tp/), the circuits can work properly. The proposed BiCMOS IFSC circuits are suitable for high-speed operations. When the capacitor load is larger than 0.6 pf; the propagation delay and the delay power product at different internal voltages are better than previous circuits under the same circuit design parameters. We also establish the relationship between the Kr=Kn/Kp ratio and the circuit area. This can avoid the trial and error step in the circuit sizing operation to reduce the power consumption.
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