基于硬件的动态可重构密码系统的VLSI实现

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI:10.1109/VLSIC.2000.852891

Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa

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引用次数: 0

摘要

实现了一种专用于64位块、128位密钥的新型基于硬件的变色龙密码系统的密码核。变色龙采用了独特的方法，它的两个32个单元，8个上下文动态可重构单元为加密过程的16次迭代中的每一次生成子密钥。所提出的密码核心已通过0.6 /spl mu/m CMOS 3lm技术集成在5.90 mm/sup / /的芯片面积内，最大吞吐量达到635 Mbps。

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VLSI implementation of dynamically reconfigurable hardware-based cryptosystem

A cipher core has been implemented, which is dedicated to the 64-bit block, 128-bit key novel hardware-based cryptosystem called Chameleon. Chameleon adopts the approach that is distinctive for its two 32-cell, 8-context dynamically reconfigurable unit to generate subkeys for each of the 16 iterations of encryption process. The proposed cipher core has been integrated in the die area of 5.90 mm/sup 2/ by means of a 0.6 /spl mu/m CMOS 3 LM technology which attains a maximum throughput of 635 Mbps.

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2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

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